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Unit kdpcitypes

Description

Unit kdpcitypes contains accompanying definitions for classes modelling different configuration spaces of PCI hardware.

Types

Overview

pPciCfg = ^TPciCfg
TBridge = record base_address0 : DWORD; base_address1 : DWORD; primary_bus : Byte; secondary_bus : Byte; subordinate_bus : Byte; secondary_latency : Byte; IO_base_low : Byte; IO_limit_low : Byte; secondary_status : Word; memory_base_low : Word; memory_limit_low : Word; prefetch_base_low : Word; prefetch_limit_low : Word; prefetch_base_high : DWORD; prefetch_limit_high : DWORD; IO_base_high : Word; IO_limit_high : Word; reserved2 : DWORD; expansion_ROM : DWORD; interrupt_line : Byte; interrupt_pin : Byte; bridge_control : Word; device_specific : array[1..48] of DWORD; last_address0 : DWORD; last_address1 : DWORD; Reserved1 : DWORD; Reserved22 : DWORD; Reserved3 : DWORD; Reserved4 : DWORD; CardDescription : array[0..199] of char; DeviceDescription : array[0..199] of char; end
TCardBus = record ExCa_base : DWORD; cap_ptr : Byte; reserved05 : Byte; secondary_status : Word; PCI_bus : Byte; CardBus_bus : Byte; subordinate_bus : Byte; latency_timer : Byte; memory_base0 : DWORD; memory_limit0 : DWORD; memory_base1 : DWORD; memory_limit1 : DWORD; IObase_0low : Word; IObase_0high : Word; IOlimit_0low : Word; IOlimit_0high : Word; IObase_1low : Word; IObase_1high : Word; IOlimit_1low : Word; IOlimit_1high : Word; interrupt_line : Byte; interrupt_pin : Byte; bridge_control : Word; subsystem_vendorID : Word; subsystem_deviceID : Word; legacy_baseaddr : DWORD; cardbus_reserved : array[1..14] of DWORD; vendor_specific : array[1..32] of DWORD; Reserved1 : DWORD; Reserved2 : DWORD; Reserved3 : DWORD; Reserved4 : DWORD; Reserved5 : DWORD; Reserved6 : DWORD; CardDescription : array[0..199] of char; DeviceDescription : array[0..199] of char; end
TCommonPci = record BAR : array[0..5] of DWORD; CardBus_CIS : DWORD; subsystem_vendorID : Word; subsystem_deviceID : Word; expansion_ROM : DWORD; cap_ptr : Byte; reserved1 : array[1..3] of Byte; reserved2 : DWORD; interrupt_line : Byte; interrupt_pin : Byte; min_grant : Byte; max_latency : Byte; device_specific : array[1..48] of DWORD; last_address0 : DWORD; last_address1 : DWORD; last_address2 : DWORD; last_address3 : DWORD; last_address4 : DWORD; last_address5 : DWORD; CardDescription : array[0..199] of char; DeviceDescription : array[0..199] of char; end
TNonBridge = record base_address0 : DWORD; base_address1 : DWORD; base_address2 : DWORD; base_address3 : DWORD; base_address4 : DWORD; base_address5 : DWORD; CardBus_CIS : DWORD; subsystem_vendorID : Word; subsystem_deviceID : Word; expansion_ROM : DWORD; cap_ptr : Byte; reserved1 : array[1..3] of Byte; reserved2 : DWORD; interrupt_line : Byte; interrupt_pin : Byte; min_grant : Byte; max_latency : Byte; device_specific : array[1..48] of DWORD; last_address0 : DWORD; last_address1 : DWORD; last_address2 : DWORD; last_address3 : DWORD; last_address4 : DWORD; last_address5 : DWORD; CardDescription : array[0..199] of char; DeviceDescription : array[0..199] of char; end
TPciCfg = record vendorID : Word; deviceID : Word; command_reg : Word; status_reg : Word; revisionID : Byte; progIF : Byte; subclass : Byte; classcode : Byte; cacheline_size : Byte; latency : Byte; header_type : Byte; BIST : Byte; case Integer of 0 : (NonBridge : TNonBridge); 1 : (Bridge : TBridge); 2 : (CardBus : TCardBus); 3 : (Common : TCommonPci); end

Description

pPciCfg = ^TPciCfg

pPciCfg = ^TPciCfg;

TBridge = record base_address0 : DWORD; base_address1 : DWORD; primary_bus : Byte; secondary_bus : Byte; subordinate_bus : Byte; secondary_latency : Byte; IO_base_low : Byte; IO_limit_low : Byte; secondary_status : Word; memory_base_low : Word; memory_limit_low : Word; prefetch_base_low : Word; prefetch_limit_low : Word; prefetch_base_high : DWORD; prefetch_limit_high : DWORD; IO_base_high : Word; IO_limit_high : Word; reserved2 : DWORD; expansion_ROM : DWORD; interrupt_line : Byte; interrupt_pin : Byte; bridge_control : Word; device_specific : array[1..48] of DWORD; last_address0 : DWORD; last_address1 : DWORD; Reserved1 : DWORD; Reserved22 : DWORD; Reserved3 : DWORD; Reserved4 : DWORD; CardDescription : array[0..199] of char; DeviceDescription : array[0..199] of char; end

type TBridge = record base_address0 : DWORD; base_address1 : DWORD; primary_bus : Byte; secondary_bus : Byte; subordinate_bus : Byte; secondary_latency : Byte; IO_base_low : Byte; IO_limit_low : Byte; secondary_status : Word; memory_base_low : Word; memory_limit_low : Word; prefetch_base_low : Word; prefetch_limit_low : Word; prefetch_base_high : DWORD; prefetch_limit_high : DWORD; IO_base_high : Word; IO_limit_high : Word; reserved2 : DWORD; expansion_ROM : DWORD; interrupt_line : Byte; interrupt_pin : Byte; bridge_control : Word; device_specific : array[1..48] of DWORD; last_address0 : DWORD; last_address1 : DWORD; Reserved1 : DWORD; Reserved22 : DWORD; Reserved3 : DWORD; Reserved4 : DWORD; CardDescription : array[0..199] of char; DeviceDescription : array[0..199] of char; end;

TCardBus = record ExCa_base : DWORD; cap_ptr : Byte; reserved05 : Byte; secondary_status : Word; PCI_bus : Byte; CardBus_bus : Byte; subordinate_bus : Byte; latency_timer : Byte; memory_base0 : DWORD; memory_limit0 : DWORD; memory_base1 : DWORD; memory_limit1 : DWORD; IObase_0low : Word; IObase_0high : Word; IOlimit_0low : Word; IOlimit_0high : Word; IObase_1low : Word; IObase_1high : Word; IOlimit_1low : Word; IOlimit_1high : Word; interrupt_line : Byte; interrupt_pin : Byte; bridge_control : Word; subsystem_vendorID : Word; subsystem_deviceID : Word; legacy_baseaddr : DWORD; cardbus_reserved : array[1..14] of DWORD; vendor_specific : array[1..32] of DWORD; Reserved1 : DWORD; Reserved2 : DWORD; Reserved3 : DWORD; Reserved4 : DWORD; Reserved5 : DWORD; Reserved6 : DWORD; CardDescription : array[0..199] of char; DeviceDescription : array[0..199] of char; end

type TCardBus = record ExCa_base : DWORD; cap_ptr : Byte; reserved05 : Byte; secondary_status : Word; PCI_bus : Byte; CardBus_bus : Byte; subordinate_bus : Byte; latency_timer : Byte; memory_base0 : DWORD; memory_limit0 : DWORD; memory_base1 : DWORD; memory_limit1 : DWORD; IObase_0low : Word; IObase_0high : Word; IOlimit_0low : Word; IOlimit_0high : Word; IObase_1low : Word; IObase_1high : Word; IOlimit_1low : Word; IOlimit_1high : Word; interrupt_line : Byte; interrupt_pin : Byte; bridge_control : Word; subsystem_vendorID : Word; subsystem_deviceID : Word; legacy_baseaddr : DWORD; cardbus_reserved : array[1..14] of DWORD; vendor_specific : array[1..32] of DWORD; Reserved1 : DWORD; Reserved2 : DWORD; Reserved3 : DWORD; Reserved4 : DWORD; Reserved5 : DWORD; Reserved6 : DWORD; CardDescription : array[0..199] of char; DeviceDescription : array[0..199] of char; end;

TCommonPci = record BAR : array[0..5] of DWORD; CardBus_CIS : DWORD; subsystem_vendorID : Word; subsystem_deviceID : Word; expansion_ROM : DWORD; cap_ptr : Byte; reserved1 : array[1..3] of Byte; reserved2 : DWORD; interrupt_line : Byte; interrupt_pin : Byte; min_grant : Byte; max_latency : Byte; device_specific : array[1..48] of DWORD; last_address0 : DWORD; last_address1 : DWORD; last_address2 : DWORD; last_address3 : DWORD; last_address4 : DWORD; last_address5 : DWORD; CardDescription : array[0..199] of char; DeviceDescription : array[0..199] of char; end

type TCommonPci = record BAR : array[0..5] of DWORD; CardBus_CIS : DWORD; subsystem_vendorID : Word; subsystem_deviceID : Word; expansion_ROM : DWORD; cap_ptr : Byte; reserved1 : array[1..3] of Byte; reserved2 : DWORD; interrupt_line : Byte; interrupt_pin : Byte; min_grant : Byte; max_latency : Byte; device_specific : array[1..48] of DWORD; last_address0 : DWORD; last_address1 : DWORD; last_address2 : DWORD; last_address3 : DWORD; last_address4 : DWORD; last_address5 : DWORD; CardDescription : array[0..199] of char; DeviceDescription : array[0..199] of char; end;

TNonBridge = record base_address0 : DWORD; base_address1 : DWORD; base_address2 : DWORD; base_address3 : DWORD; base_address4 : DWORD; base_address5 : DWORD; CardBus_CIS : DWORD; subsystem_vendorID : Word; subsystem_deviceID : Word; expansion_ROM : DWORD; cap_ptr : Byte; reserved1 : array[1..3] of Byte; reserved2 : DWORD; interrupt_line : Byte; interrupt_pin : Byte; min_grant : Byte; max_latency : Byte; device_specific : array[1..48] of DWORD; last_address0 : DWORD; last_address1 : DWORD; last_address2 : DWORD; last_address3 : DWORD; last_address4 : DWORD; last_address5 : DWORD; CardDescription : array[0..199] of char; DeviceDescription : array[0..199] of char; end

type TNonBridge = record base_address0 : DWORD; base_address1 : DWORD; base_address2 : DWORD; base_address3 : DWORD; base_address4 : DWORD; base_address5 : DWORD; CardBus_CIS : DWORD; subsystem_vendorID : Word; subsystem_deviceID : Word; expansion_ROM : DWORD; cap_ptr : Byte; reserved1 : array[1..3] of Byte; reserved2 : DWORD; interrupt_line : Byte; interrupt_pin : Byte; min_grant : Byte; max_latency : Byte; device_specific : array[1..48] of DWORD; last_address0 : DWORD; last_address1 : DWORD; last_address2 : DWORD; last_address3 : DWORD; last_address4 : DWORD; last_address5 : DWORD; CardDescription : array[0..199] of char; DeviceDescription : array[0..199] of char; end;

TPciCfg = record vendorID : Word; deviceID : Word; command_reg : Word; status_reg : Word; revisionID : Byte; progIF : Byte; subclass : Byte; classcode : Byte; cacheline_size : Byte; latency : Byte; header_type : Byte; BIST : Byte; case Integer of 0 : (NonBridge : TNonBridge); 1 : (Bridge : TBridge); 2 : (CardBus : TCardBus); 3 : (Common : TCommonPci); end

type TPciCfg = record vendorID : Word; deviceID : Word; command_reg : Word; status_reg : Word; revisionID : Byte; progIF : Byte; subclass : Byte; classcode : Byte; cacheline_size : Byte; latency : Byte; header_type : Byte; BIST : Byte; case Integer of 0 : (NonBridge : TNonBridge); 1 : (Bridge : TBridge); 2 : (CardBus : TCardBus); 3 : (Common : TCommonPci); end;

Constants

Overview

PCI_BASE_ADDR0 = $10
PCI_BASE_ADDR1 = $14
PCI_BASE_ADDR2 = $18
PCI_BASE_ADDR3 = $1c
PCI_BASE_ADDR4 = $20
PCI_BASE_ADDR5 = $24
PCI_BASE_ADDRESS_IO_MASK = $fffffffc
PCI_BASE_ADDRESS_MEM_MASK = $fffffff0
PCI_BASE_ADDRESS_SPACE_IO = $01
PCI_BASE_ADDRESS_SPACE_MEMORY = $00
PCI_BIST = $0f
PCI_BIST_CAPABLE = $80
PCI_BIST_CODE_MASK = $0f
PCI_BIST_START = $40
PCI_CACHE_LINE_SIZE = $0c
PCI_CAPABILITY_LIST = $34
PCI_CARDBUS_CIS = $28
PCI_CLASS_DEVICE = $0a
PCI_CLASS_PROG = $09
PCI_CLASS_REVISION = $08
PCI_COMMAND = $04
PCI_COMMAND_FAST_BACK = $200
PCI_COMMAND_INVALIDATE = $10
PCI_COMMAND_IO = $1
PCI_COMMAND_MASTER = $4
PCI_COMMAND_MEMORY = $2
PCI_COMMAND_PARITY = $40
PCI_COMMAND_SERR = $100
PCI_COMMAND_SPECIAL = $8
PCI_COMMAND_VGA_PALETTE = $20
PCI_COMMAND_WAIT = $80
PCI_HEADER_TYPE = $0e
PCI_HEADER_TYPE_BRIDGE = 1
PCI_HEADER_TYPE_CARDBUS = 2
PCI_HEADER_TYPE_NORMAL = 0
PCI_INTERRUPT_LINE = $3c
PCI_INTERRUPT_PIN = $3d
PCI_LATENCY_TIMER = $0d
PCI_MAX_LAT = $3f
PCI_MIN_GNT = $3e
PCI_REG40 = $40
PCI_REG44 = $44
PCI_REG48 = $48
PCI_REG4C = $4C
PCI_REG50 = $50
PCI_REG54 = $54
PCI_REG58 = $58
PCI_REG5C = $5C
PCI_REG60 = $60
PCI_REG64 = $64
PCI_REG68 = $68
PCI_REG6C = $6C
PCI_REG70 = $70
PCI_REG74 = $74
PCI_REG78 = $78
PCI_REG7C = $7C
PCI_REG80 = $80
PCI_REG84 = $84
PCI_REG88 = $88
PCI_REG8C = $8C
PCI_REG90 = $90
PCI_REG94 = $94
PCI_REG98 = $98
PCI_REG9C = $9C
PCI_REGA0 = $A0
PCI_REGA4 = $A4
PCI_REGA8 = $A8
PCI_REGAC = $AC
PCI_REGB0 = $B0
PCI_REGB4 = $B4
PCI_REGB8 = $B8
PCI_REGBC = $BC
PCI_REGC0 = $C0
PCI_REGC4 = $C4
PCI_REGC8 = $C8
PCI_REGCC = $CC
PCI_REGD0 = $D0
PCI_REGD4 = $D4
PCI_REGD8 = $D8
PCI_REGDC = $DC
PCI_REGE0 = $E0
PCI_REGE4 = $E4
PCI_REGE8 = $E8
PCI_REGEC = $EC
PCI_REGF0 = $F0
PCI_REGF4 = $F4
PCI_REGF8 = $F8
PCI_REGFC = $FC
PCI_REVISION_ID = $08
PCI_ROM_ADDRESS = $30
PCI_ROM_ADDRESS_ENABLE = $01
PCI_ROM_ADDRESS_MASK = $FFFFF800
PCI_STATUS = $06
PCI_STATUS_66MHZ = $20
PCI_STATUS_CAP_LIST = $10
PCI_STATUS_DETECTED_PARITY = $8000
PCI_STATUS_DEVSEL_FAST = $000
PCI_STATUS_DEVSEL_MASK = $600
PCI_STATUS_DEVSEL_MEDIUM = $200
PCI_STATUS_DEVSEL_SLOW = $400
PCI_STATUS_FAST_BACK = $80
PCI_STATUS_PARITY = $100
PCI_STATUS_REC_MASTER_ABORT = $2000
PCI_STATUS_REC_TARGET_ABORT = $1000
PCI_STATUS_SIG_SYSTEM_ERROR = $4000
PCI_STATUS_SIG_TARGET_ABORT = $800
PCI_STATUS_UDF = $40
PCI_SUBSYSTEM_ID = $2e
PCI_SUBSYSTEM_VENDOR_ID = $2c

Description

PCI_BASE_ADDR0 = $10

address space 0 $10

PCI_BASE_ADDR1 = $14

address space 1 $14

PCI_BASE_ADDR2 = $18

address space 2 $18

PCI_BASE_ADDR3 = $1c

address space 3 $1c

PCI_BASE_ADDR4 = $20

address space 4 $20

PCI_BASE_ADDR5 = $24

address space 5 $24

PCI_BASE_ADDRESS_IO_MASK = $fffffffc

$FFFFFFFC

PCI_BASE_ADDRESS_MEM_MASK = $fffffff0

$FFFFFFF0

PCI_BASE_ADDRESS_SPACE_IO = $01

$01

PCI_BASE_ADDRESS_SPACE_MEMORY = $00

$00

PCI_BIST = $0f

8 bits built-in self-test

PCI_BIST_CAPABLE = $80

1 if BIST capable

PCI_BIST_CODE_MASK = $0f

Return result

PCI_BIST_START = $40

1 to start BIST, 2 secs or less

PCI_CACHE_LINE_SIZE = $0c

8 bits

PCI_CAPABILITY_LIST = $34

Offset of first capability list entry

PCI_CARDBUS_CIS = $28

$28

PCI_CLASS_DEVICE = $0a

Device class

PCI_CLASS_PROG = $09

Reg. Level Programming Interface

PCI_CLASS_REVISION = $08

High 24 bits are class, low 8 revision

PCI_COMMAND = $04

16 bits

PCI_COMMAND_FAST_BACK = $200

Enable back-to-back writes

PCI_COMMAND_INVALIDATE = $10

Use memory write and invalidate

PCI_COMMAND_IO = $1

Enable response in I/O space

PCI_COMMAND_MASTER = $4

Enable bus mastering

PCI_COMMAND_MEMORY = $2

Enable response in Memory space

PCI_COMMAND_PARITY = $40

Enable parity checking

PCI_COMMAND_SERR = $100

Enable SERR

PCI_COMMAND_SPECIAL = $8

Enable response to special cycles

PCI_COMMAND_VGA_PALETTE = $20

Enable palette snooping

PCI_COMMAND_WAIT = $80

Enable address/data stepping

PCI_HEADER_TYPE = $0e

8 bits

PCI_HEADER_TYPE_BRIDGE = 1

1

PCI_HEADER_TYPE_CARDBUS = 2

2

PCI_HEADER_TYPE_NORMAL = 0

0

PCI_INTERRUPT_LINE = $3c

8 bits

PCI_INTERRUPT_PIN = $3d

8 bits

PCI_LATENCY_TIMER = $0d

8 bits

PCI_MAX_LAT = $3f

8 bits

PCI_MIN_GNT = $3e

8 bits

PCI_REG40 = $40

$40

PCI_REG44 = $44

$44

PCI_REG48 = $48

$48

PCI_REG4C = $4C

$4C

PCI_REG50 = $50

$50

PCI_REG54 = $54

$54

PCI_REG58 = $58

$58

PCI_REG5C = $5C

$5C

PCI_REG60 = $60

$60

PCI_REG64 = $64

$64

PCI_REG68 = $68

$68

PCI_REG6C = $6C

$6C

PCI_REG70 = $70

$70

PCI_REG74 = $74

$74

PCI_REG78 = $78

$78

PCI_REG7C = $7C

$7C

PCI_REG80 = $80

$80

PCI_REG84 = $84

$84

PCI_REG88 = $88

$88

PCI_REG8C = $8C

$8C

PCI_REG90 = $90

$90

PCI_REG94 = $94

$94

PCI_REG98 = $98

$98

PCI_REG9C = $9C

$9C

PCI_REGA0 = $A0

$A0

PCI_REGA4 = $A4

$A4

PCI_REGA8 = $A8

$A8

PCI_REGAC = $AC

$AC

PCI_REGB0 = $B0

$B0

PCI_REGB4 = $B4

$B4

PCI_REGB8 = $B8

$B8

PCI_REGBC = $BC

$BC

PCI_REGC0 = $C0

$C0

PCI_REGC4 = $C4

$C4

PCI_REGC8 = $C8

$C8

PCI_REGCC = $CC

$CC

PCI_REGD0 = $D0

$D0

PCI_REGD4 = $D4

$D4

PCI_REGD8 = $D8

$D8

PCI_REGDC = $DC

$DC

PCI_REGE0 = $E0

$E0

PCI_REGE4 = $E4

$E4

PCI_REGE8 = $E8

$E8

PCI_REGEC = $EC

$EC

PCI_REGF0 = $F0

$F0

PCI_REGF4 = $F4

$F4

PCI_REGF8 = $F8

$F8

PCI_REGFC = $FC

$FC

PCI_REVISION_ID = $08

Revision ID

PCI_ROM_ADDRESS = $30

Bits 31..11 are address, 10..1 reserved

PCI_ROM_ADDRESS_ENABLE = $01

$01

PCI_ROM_ADDRESS_MASK = $FFFFF800

(~0x7FFUL)

PCI_STATUS = $06

16 bits

PCI_STATUS_66MHZ = $20

Support 66 Mhz PCI 2.1 bus

PCI_STATUS_CAP_LIST = $10

Support Capability List

PCI_STATUS_DETECTED_PARITY = $8000

Set on parity error

PCI_STATUS_DEVSEL_FAST = $000

$000

PCI_STATUS_DEVSEL_MASK = $600

DEVSEL timing

PCI_STATUS_DEVSEL_MEDIUM = $200

$200

PCI_STATUS_DEVSEL_SLOW = $400

$400

PCI_STATUS_FAST_BACK = $80

Accept fast-back to back

PCI_STATUS_PARITY = $100

Detected parity error

PCI_STATUS_REC_MASTER_ABORT = $2000

Set on master abort

PCI_STATUS_REC_TARGET_ABORT = $1000

Master ack of double quotes

PCI_STATUS_SIG_SYSTEM_ERROR = $4000

Set when we drive SERR

PCI_STATUS_SIG_TARGET_ABORT = $800

Set on target abort

PCI_STATUS_UDF = $40

Support User Definable Features [obsolete]

PCI_SUBSYSTEM_ID = $2e

$2E

PCI_SUBSYSTEM_VENDOR_ID = $2c

$2C

Authors

ETSoft Tenzor.Net (etsoft@tenzor.net)

CHIN T.

Created

01 May 2004

Last Modified

05 February 2005